`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:06:56 05/22/2020 
// Design Name: 
// Module Name:    MA 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module MA(
    input [11:0] MA_a,
    input [11:0] MA_b,
    output [11:0] MA_s
    );

wire [11:0] CSA_cin0;
wire [11:0] CSA_cin;
wire [11:0] CSA_sum0;
wire [11:0] s0;
wire [11:0] s1;
wire sel0;
wire sel;
wire default_sel;// useless

//assign CSA_cin = CSA_cin0<<1;

assign CSA_cin = {CSA_cin0[10:0],1'b0};
assign sel = sel0 | CSA_cin0[11];
assign MA_s = sel? s0 : s1;

CSA CSA0 (
    .CSA_a(MA_a), 
    .CSA_b(MA_b), 
    .CSA_cin(CSA_cin0), 
    .CSA_sum(CSA_sum0)
    );

CPA CPA0 (
    .CPA_a(CSA_cin), 
    .CPA_b(CSA_sum0), 
    .CPA_sum(s0), 
    .CPA_cout(sel0)
    );

CPA CPA1 (
    .CPA_a(MA_a), 
    .CPA_b(MA_b), 
    .CPA_sum(s1), 
    .CPA_cout(default_sel)
    );


endmodule
